1. Field of the Invention
The present invention relates to manufacturing small dimension features of objects, such as integrated circuits, using photolithographic masks. More particularly, the present invention relates to phase shift masking of complex layouts for integrated circuits and similar objects.
2. Description of Related Art
Phase shift masking has been applied to create small dimension features in integrated circuits. Typically the features have been limited to selected elements of the design, which have a small, critical dimension. See, for example, U.S. Pat. No. 5,766,806.
Although manufacturing of small dimension features in integrated circuits has resulted in improved speed and performance, it is desirable to apply phase shift masking more extensively in the manufacturing of such devices. However, the extension of phase shift masking to more complex designs results in a large increase in the complexity of the mask layout problem. For example, when laying out phase shift windows on dense designs, phase conflicts will occur. One type of phase conflict is a location in the layout at which two phase shift windows having the same phase are laid out in proximity to a feature to be exposed by the masks, such as by overlapping of the phase shift windows intended for implementation of adjacent lines in the exposure pattern. If the phase shift windows have the same phase, then they do not result in the optical interference necessary to create the desired feature. Thus, it is necessary to prevent inadvertent layout of phase shift windows in phase conflict near features to be formed in the layer defined by the mask.
In the design of a single integrated circuit, millions of features may be laid out. The burden on data processing resources for iterative operations over such large numbers of features can be huge, and in some cases makes the iterative operation impractical. The layout of phase shift windows and the assignment of phase shift values to such windows, for circuits in which a significant amount of the layout is accomplished by phase shifting, is one such iterative operation which has been impractical using prior art techniques.
Phase shifting layouts for memory cells have been developed that phase shift gate portions of the memory design for improved performance.
Because of these and other complexities, implementation of a phase shift masking technology for complex designs will require improvements in the approach to the design of phase shift masks.
Methods and apparatuses for fully defining static random access memory (SRAM) using phase shifting layouts are described. By producing the SRAM memory using a xe2x80x9cfull phasexe2x80x9d mask, yield can be improved at smaller sizes (relative to using the same lithographic process with a non-phase shifting mask, particularly the wavelength of light, xcex), integrated circuit density is improved by tighter packing of smaller memory cells, and also the performance of the memory can be improved.
The approach includes identifying that a layout includes SRAM cells and defining phase shifting regions in a mask description to fully define the SRAM cells. The identification may include an automated detection of layout patterns that correspond to SRAM cells, parameterized shape detection, user identification of SRAM cells either interactively through a user interface and/or through input parameters, and/or other identification approaches.
A region around the layout shapes for an SRAM cell can be identified where phase shifters will be placed in the mask definition. By placing shifters in this region, destructive interference of light of opposite phases will cause definition of the pattern. However, it is necessary to break, or cut, the phase windows in the region to fully permit definition of the feature using phase shifters of opposite phases on opposing edges of the layout shapes of the SRAM cell.
The cuts can be light transmissive phase shifters as well at intermediate phase values (continuous, 90, 60-120) relative to the primary phase shifters (0 and 180).
The portion of the SRAM memory cell layout that is more difficult to define using phase shifting generally comprises two T-shapes (xe2x80x9cTxe2x80x2sxe2x80x9d) with off-centered bars interlaced with one another. There are contacts at the base of the bars and four transistors on either end of the top of the T. There are two additional transistors disposed above the interlaced T portion.
Several locations where cuts will be admitted are used by embodiments of the invention: contact to contact, inside corners of the T""s to field, back of T""s to back of adjacent T""s, contacts to field, and corners of T""s to contacts. By selecting one or more of these cutting locations a phase shifting layout of the SRAM memory cell is possible.
Most mask layouts will select a single cutting pattern for all SRAM memory cells in a particular area. For example, the cutting pattern of using the inside corners of the T""s to field together with the back of T""s to back of adjacent T""s for all SRAM memory cells could be used for all of the SRAM memory cells in a given integrated circuit.
Additionally, attention may be given to ensuring that corresponding features from one SRAM memory cell to another are defined using the same phase ordering. For example if the phase shifter on the left a given transistor is phase 0 and the one on the right is 180, then it may be desirable to ensure that the phase shifter on the left of the corresponding transistor on another SRAM memory cell is 0 and the one on the right is 180. This ensures consistency in the SRAM memory cell layout even if there is a light intensity imbalance between 0 and 180 degree phase shifters.
Embodiments of the invention can be viewed as methods of manufacturing an integrated circuit. Embodiments of the invention include phase shifting and/or complementary trim masks for use in defining a layer of material in a photolithographic process.